In this lesson, you’ll start building your own Minimal Real-time Operating System (MiROS), where you’ll automate the context switch.
in the last lesson, you encountered the concept of a Real-Time Operating System (RTOS), and you worked out a manual procedure of switching the context from one thread to another. In this lesson, you’ll start building your own Minimal Real-time Operating System (MiROS) where you’ll automate the context switch.
Lesson 23 – RTOS: Automating the context switch
As I firmly believe in learning by doing, I invite you to build the MiROS RTOS with me in the process known as pair programming. We start by adding a new group to the project with a header and source files. Then, we gradually fill in the details, primarily by copying, pasting, and modifying the snippets of code you had already. By consistently having two side-by-side views, we can more easily figure out the kernel API (Application Programming Interface) in one view while immediately trying to use the API in the other. I hope you learn something useful if you’ve never worked like that.
The PendSV Exception
From the last lesson, you should remember that the RTOS context switch “hijacks” the interrupt handling mechanism already available in the CPU. Specifically, by the end of an ISR (such as the SysTick_Handler in the video), you “trick” the CPU into returning to a different thread than the one preempted initially. For that, you’d have to add the context switch code to every ISR, which is inconvenient.
In ARM Cortex-M, ISRs can also nest (preempt each other), so only the return from the last nested interrupt (back to the thread level) should perform a context switch. The problem is that the order of ISR preemption changes dynamically at runtime, so you generally don’t know which one will be the last.
An elegant solution employed in virtually all RTOSs for ARM Cortex-M is to take advantage of the same interrupt nesting mechanism that created the problem in the first place. Specifically, Cortex-M provides the PendSV exception (Pend Service Call) , which you can program to perform the context switch and configure with the lowest interrupt priority (0xFF). When the RTOS detects the need to switch the context, it can pend the PendSV exception. The interrupt prioritization ensures that PendSV will be the last ISR to run just before returning to the thread level. Moreover, the NVIC in ARM Cortex-M has a built-in hardware optimization called “tail chaining,” which eliminates the overhead of exiting one interrupt (eg, SysTick) and entering PendSV, so the context switch is performed with minimal overhead.
Coding the Context-Switch in Assembly
The context switch in PendSV_Handler() cannot be coded in standard C because it needs to manipulate the Stack Pointer (SP) as well as push and pop CPU registers. But you can still leverage the C compiler to give you a good starting point for your assembly programming. The video shows how to code an “approximate” algorithm in C and then utilize the generated machine code from the disassembly view.
The MiROS kernel starts to take shape , but the schedule is still performed manually. In the next lesson, you will extend the MiROS RTOS with a straightforward scheduling policy called round-robin. That way, you will implement a time-sharing system on your TivaC LaunchPad. Stay tuned!
 Miro Samek, MiROS (Minimal Real-Time Operating System)GitHub
 Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors, 3rd Edition”ISBN: 978-0124080829
|Dr. Miro M. Samek is the creator of the open source QP real-time embedded framework and the freeware QM graphical model-based design tool. He is also the founder and CEO of Quantum Leaps — the provider of modern embedded software based on active objects and hierarchical state machines as well as tools for visual modeling, automatic code generation, and unit testing of deeply embedded software. Miro teaches the popular YouTube “Modern Embedded Systems Programming” video course on which this article series is based.|
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